This sailing ASIC development system is used for validation and verification of the designed IP cores and ASIC before the GDSII file is handed out for production. The platform with FPGA can also be used for various SOC projects. The JTAG cable and power supply module promise stable performance.

• FPGA daughter board, sailing development mother board.
• Optional PCI interface.
• Sailing S698 processor and SOC IP.
• Supports EOS and IDE.